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IRIS è il sistema di gestione integrata dei dati della ricerca (persone, progetti, pubblicazioni, attività) adottato dall'Università degli Studi di Cagliari dal mese di luglio 2015.

Mostra risultati da 1 a 20 di 119
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TitoloData di pubblicazioneAutore(i)RivistaEditore
A modular digital VLSI architecture for stereo-depth estimation in industrial application1999Alimonda A; Carta SM; Raffo L
44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture2002Atzori E; CARTA SM; Raffo LELECTRONICS LETTERS
Processing time saving in low power voice coding applications using synchronous reconfigurable co-processing architecture2002Carta SM; Raffo L
A synthesis oriented design library for Network On Chip2005S.STERGIOU; F.ANGIOLINI; P.MELONI; D.BERTOZZI; L.BENINI; CARTA S.M.; L.RAFFO
Networks on Chips: A Synthesis Perspective2005F. ANGIOLINI; P. MELONI; D. BERTOZZI; L. BENINI; CARTA S.M.; L. RAFFO
Routing Aware Switch Hardware Customization for Networks on Chips2006MELONI P; MURALI S; CARTA S; CAMPLANI M; RAFFO L; DE MICHELI G
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness2006F.ANGIOLINI; P.MELONI; CARTA S.M.; L. BENINI; L.RAFFO
Reconfigurable Coprocessor for Multimedia Application Domain2006CARTA S; PANI D; RAFFO LJOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Elaboration in MPSoCs2006ALIMONDA A; ACQUAVIVA A; CARTA SM; PISANO A
Non-Linear Feedback Control for Energy Efficient On-Chip Streaming Computation2006ALIMONDA A; CARTA SM; ACQUAVIVA A; PISANO A
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems-on-Chips2006MURALI S; MELONI P; ANGIOLINI F; ATIENZA D; CARTA S; BENINI L; DE MICHELI G; RAFFO L
Exploiting Memory-Boundedness in Energy-Efficient Hard Real-Time Scheduling2006MARCO SPIGA; MATTIA SPIGA; ALIMONDA A; SALVATORE CARTA; FRANCESCO AYMERICH; ANDREA ACQUAVIVA
Designing Application-Specific Networks on Chips with Floorplan Information2006S. MURALI; P. MELONI; F. ANGIOLINI; D. ATIENZA; CARTA S.M.; L. BENINI; G. DE MICHELI; L. RAFFO
Area and Power Modeling Methodologies for Networks-on-Chip2006P. MELONI; CARTA S.M.; R. ARGIOLAS; L. RAFFO; F. ANGIOLINI
Automatic application partitioning on FPGA/CPU systems based on detailed low-level information2006BUSONERA G; CARTA S; MARONGIU A; RAFFO L
Design Application-Specific Networks on Chips with Floorplan Information2006MURALI S; MELONI P; ANGIOLINI F; ATIENZA D; CARTA S; BENINI L; DE MICHELI G; RAFFO L
Impact of Task Migration on Streaming Multimedia for Embedded Multiprocessors: A Quantitative Evaluation2007M. PITTAU; A. ALIMONDA; CARTA S.M.; A.ACQUAVIVA
On the impact of serializatioin on the cache performances in Network-on-Chip based MPSoCs2007MELONI P; BUSONERA G; CARTA SM; RAFFO L
Multi-Processor Operating System Emulation Framework with Thermal Feedback for Systems-on-Chip2007CARTA SM; ACQUAVIVA A; DEL VALLE PG; PITTAU M; ATIENZA D; RINCON F; BENINI L; DE MICHELI G; MENDI...AS JM
A Control Theoretic Approach to Energy Efficient Pipelined Computation in MPSoCs2007Carta, Salvatore; Alimonda, A; Pisano, Alessandro; Acquaviva, A; BeniniACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS
   
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