Prodotti della ricerca
UNICA IRIS Institutional Research Information System
IRIS è il sistema di gestione integrata dei dati della ricerca (persone, progetti, pubblicazioni, attività) adottato dall'Università degli Studi di Cagliari dal mese di luglio 2015.
| Titolo | Data di pubblicazione | Autore(i) | Rivista | Editore |
|---|---|---|---|---|
| MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation | 2016 | Meloni, Paolo; Palumbo, Francesca; Rubattu, Claudio; Tuveri, Giuseppe; Pani, Danilo; Raffo, Luigi | MICROPROCESSORS AND MICROSYSTEMS | |
| Power and clock gating modelling in coarse grained reconfigurable systems | 2016 | Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca | ACM | |
| Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures | 2016 | Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi | JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING | |
| Exploring custom heterogeneous MPSoCs for real-time neural signal decoding | 2015 | Meloni P; Tuveri G; Pani D; Raffo L; Palumbo F | IEEE | |
| Power Modelling for Saving Strategies in Coarse Grained Reconfigurable Systems | 2015 | Fanni T; Sau C; Meloni P; Raffo L; Palumbo F | ||
| Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain | 2015 | Sau C; Fanni L; Meloni P; Raffo L; Palumbo F | ||
| Online process transformation for polyhedral process networks in shared-memory MPSoCs | 2014 | Meloni P; Tuveri G; Raffo L; Loi I; Conti F | IEEE | |
| A custom MPSoC architecture with integrated power management for real-time neural signal decoding | 2014 | Carta N; Meloni P; Tuveri G; Pani D; Raffo L | IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS | |
| A stream buffer mechanism for pervasive splitting transformations on polyhedral process networks | 2014 | Meloni P; Tuveri G; Raffo L; Loi I; Conti F | ACM INTERNATIONAL CONFERENCE PROCEEDINGS SERIES | ACM Digital Library |
| The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms | 2014 | Palumbo F; Carta N; Pani D; Meloni P; Raffo L | JOURNAL OF REAL-TIME IMAGE PROCESSING | |
| A runtime adaptive H.264 video-decoding MPSoC platform | 2013 | Tuveri G; Secchi S; Meloni P; Raffo L; Cannella E | IEEE | |
| A low overhead self-adaptation technique for KPN applications on NoC-based MPSoCs | 2013 | Derin O; Ramankutty P; Meloni P; Tuveri G | IEEE | |
| A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project | 2013 | Derin O; Cannella E; Tuveri G; Meloni P; Stefanov T; Fiorin L; Raffo L; Sami M | MICROPROCESSORS AND MICROSYSTEMS | |
| ASAM: Automatic architecture synthesis and application mapping | 2013 | Jozwiak L; Lindwer M; Corvino R; Meloni P; Micconi L; Madsen J; Diken E; Gangadharan D; Jordans R...; Pomata S; Pop P; Tuveri G; Raffo L; Notarangelo G | MICROPROCESSORS AND MICROSYSTEMS | |
| Enabling fast ASIP design space exploration: An FPGA-based runtime reconfigurable prototyper | 2012 | Meloni P; Pomata S; Tuveri G; Secchi S; Raffo L; Lindwer M | VLSI DESIGN | |
| System adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project approach | 2012 | Meloni P; Tuveri G; Raffo L; Cannella E; Stefanov T; Derin O; Fiorin L; Sami M | IEEE | |
| FPGA-Based Emulation Support for Design Space Exploration | 2012 | Meloni P; Secchi S; Raffo L | John Wiley & Sons, Inc. | |
| Exploiting binary translation for fast ASIP design space exploration on FPGAs | 2012 | Pomata S; Meloni P; Tuveri G; Raffo L; Lindwer M | IEEE | |
| Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems | 2012 | Meloni P; Pomata S; Raffo L; Piscitelli R; Pimentel AD | ||
| Adaptivity support for MPSoCs based on process migration in polyhedral process networks | 2012 | Cannella E; Derin O; Meloni P; Tuveri G; Stefanov T | VLSI DESIGN |
