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IRIS è il sistema di gestione integrata dei dati della ricerca (persone, progetti, pubblicazioni, attività) adottato dall'Università degli Studi di Cagliari dal mese di luglio 2015.

Mostra risultati da 21 a 40 di 51
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TitoloData di pubblicazioneAutore(i)RivistaEditore
Adaptable AES implementation with power-gating support2016Banik, Subhadeep; Bogdanov, Andrey; Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca;... Regazzoni, FrancescoAssociation for Computing Machinery, Inc
On-the-fly adaptivity for process networks over shared-memory platforms2016Tuveri, Giuseppe; Meloni, Paolo; Palumbo, Francesca; Giovanni, Pietro Seu; Loi, Igor; Conti, Fran...cesco; Raffo, LuigiMICROPROCESSORS AND MICROSYSTEMS
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC2016Palumbo, Francesca; Sau, Carlo; Evangelista, Davide; Meloni, Paolo; Pelcat, Maxime; Raffo, LuigiIFAC-PAPERSONLINEElsevier B.V.
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures2016Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, LuigiJOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING
Automated power gating methodology for dataflow-based reconfigurable systems2015FANNI, TIZIANA; SAU, CARLO; RAFFO, LUIGI; PALUMBO, FRANCESCAAssociation for Computing Machinery
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding2015Meloni P; Tuveri G; Pani D; Raffo L; Palumbo FIEEE
Power modelling for saving strategies in coarse grained reconfigurable systems2015Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, FrancescaIEEE
Coarse-grained reconfiguration: dataflow-based power management2015Palumbo F; Sau C; Raffo LIET COMPUTERS & DIGITAL TECHNIQUES
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain2015Sau, Carlo; Fanni, L; Meloni, Paolo; Raffo, Luigi; Palumbo, FrancescaIEEE
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case2014Sau C; Raffo L; Palumbo F; Bezati E; Casale-Brunet S; Mattavelli MIEEE
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms2014Palumbo F; Carta N; Pani D; Meloni P; Raffo LJOURNAL OF REAL-TIME IMAGE PROCESSING
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy2014Palumbo F; Sau C; Raffo LIEEE
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units2014Sau C; Palumbo FIEEE
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms2013Sau C; Palumbo F; Raffo L
DSE and profiling of multi-context coarse-grained reconfigurable systems2013Palumbo F; Sau C; Raffo LIEEE
A coarse-grained reconfigurable approach for low-power spike sorting architectures2013Carta N; Sau C; Pani D; Palumbo F; Raffo LInstitute of Electrical and Electronics Engineers (IEEE)
Design IP Faster: Introducing the C~ High-Level Language2012Wipliez M; Siret N; Carta N; Palumbo F; Raffo L
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture2012Palumbo F; Pani D; Congiu A; Raffo LACM
Multi-purpose systems: A novel dataflow-based generation and mapping strategy2012Nezan JF; Siret N; Wipliez M; Palumbo F; Raffo L
A nature-inspired adaptive floating-point coprocessing system2012Sau C; Pani D; Palumbo F; Raffo LIEEE
   
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