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IRIS è il sistema di gestione integrata dei dati della ricerca (persone, progetti, pubblicazioni, attività) adottato dall'Università degli Studi di Cagliari dal mese di luglio 2015.

Mostra risultati da 1 a 19 di 19
TitoloData di pubblicazioneAutore(i)RivistaEditore
An FPGA platform for real-time simulation of spiking neuronal networks2017Pani, Danilo; Meloni, Paolo; Tuveri, Giuseppe; Palumbo, Francesca; Massobrio, Paolo; Raffo, LuigiFRONTIERS IN NEUROSCIENCE
A closed-loop system for neural networks analysis through high density MEAs2017Seu, Giovanni Pietro; Angotzi, Gian Nicola; Tuveri, Giuseppe; Raffo, Luigi; Berdondini, Luca; Mac...cione, Alessandro; Meloni, PaoloInstitute of Electrical and Electronics Engineers Inc.
On-FPGA real-time processing of biological signals from high-density MEAs: A design space exploration2017Seu, Giovanni Pietro; Angotzi, Gian Nicola; Tuveri, Giuseppe; Raffo, Luigi; Berdondini, Luca; Mac...cione, Alessandro; Meloni, PaoloInstitute of Electrical and Electronics Engineers Inc.
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation2016Meloni, Paolo; Palumbo, Francesca; Rubattu, Claudio; Tuveri, Giuseppe; Pani, Danilo; Raffo, LuigiMICROPROCESSORS AND MICROSYSTEMS
On-the-fly adaptivity for process networks over shared-memory platforms2016Tuveri, Giuseppe; Meloni, Paolo; Palumbo, Francesca; Giovanni, Pietro Seu; Loi, Igor; Conti, Fran...cesco; Raffo, LuigiMICROPROCESSORS AND MICROSYSTEMS
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding2015Meloni P; Tuveri G; Pani D; Raffo L; Palumbo FIEEE
A stream buffer mechanism for pervasive splitting transformations on polyhedral process networks2014Meloni P; Tuveri G; Raffo L; Loi I; Conti FACM INTERNATIONAL CONFERENCE PROCEEDINGS SERIESACM Digital Library
A custom MPSoC architecture with integrated power management for real-time neural signal decoding2014Carta N; Meloni P; Tuveri G; Pani D; Raffo LIEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
Online process transformation for polyhedral process networks in shared-memory MPSoCs2014Meloni P; Tuveri G; Raffo L; Loi I; Conti FIEEE
Integrated support for Adaptivity and Fault-tolerance in MPSoCs3-mag-2013Università degli Studi di Cagliari
A runtime adaptive H.264 video-decoding MPSoC platform2013Tuveri G; Secchi S; Meloni P; Raffo L; Cannella EIEEE
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project2013Derin O; Cannella E; Tuveri G; Meloni P; Stefanov T; Fiorin L; Raffo L; Sami MMICROPROCESSORS AND MICROSYSTEMS
ASAM: Automatic architecture synthesis and application mapping2013Jozwiak L; Lindwer M; Corvino R; Meloni P; Micconi L; Madsen J; Diken E; Gangadharan D; Jordans R...; Pomata S; Pop P; Tuveri G; Raffo L; Notarangelo GMICROPROCESSORS AND MICROSYSTEMS
A low overhead self-adaptation technique for KPN applications on NoC-based MPSoCs2013Derin O; Ramankutty P; Meloni P; Tuveri GIEEE
ASAM: Automatic Architecture Synthesis and Application Mapping 2012Jozwiak L.; Lindwer M.; Corvino R; Meloni P; Micconi L; Madsen J; Diken E; Gangadharan D; Jordans... R; Pomata S; Pop P; Tuveri G; Raffo LIEEE
Adaptivity support for MPSoCs based on process migration in polyhedral process networks2012Cannella E; Derin O; Meloni P; Tuveri G; Stefanov TVLSI DESIGN
System adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project approach2012Meloni P; Tuveri G; Raffo L; Cannella E; Stefanov T; Derin O; Fiorin L; Sami MIEEE
Enabling fast ASIP design space exploration: An FPGA-based runtime reconfigurable prototyper2012Meloni P; Pomata S; Tuveri G; Secchi S; Raffo L; Lindwer MVLSI DESIGN
Exploiting binary translation for fast ASIP design space exploration on FPGAs2012Pomata S; Meloni P; Tuveri G; Raffo L; Lindwer MIEEE
   
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